In certain applications, such as the management of the memory of a data processing system, a cache is utilized to maintain associated information which has different periods of utility. For example, in the paged memory management unit (PMMU) described in the several copending applications cited above, logical-to-physical address translators are maintained in a translator cache. Often, it is desired to assure rapid access to certain code/data pages. This in turn requires that the translators for these pages be available in the cache for the required period of time. One solution has been to associate with each translator in the cache a lock indicator which, when set, will preclude removal of the translator in order to make room for a different transistor. When a given page is no longer needed, the PMMU can be instructed by the processor to reset the lock indicator for the translator for that page, thereby making this translator a candidate for replacement.
In general, prior art systems have imposed the burden of locking specific translators in the translation cache upon the operating system. For example, in U.S. Pat. No. 4,084,226, translators are individually locked or unlocked by the memory management unit in response to receiving direct commands from the processor. (See, for example, lines 32-34 of column 68). However, this technique requires the operating system to intervene in the translation process whenever a translator needs to be locked in the translation cache.